Area-efficient High-throughput Vlsi Architecture for Map-based Turbo Equalizer

We present an area-efficient MAP-based turbo equalizer VLSI architecture by proposing a symbol-based soft-input softoutput (SISO) kernel which processes one multi-bit symbol in every clock cycle. The symbol-based SISO hardware can be shared by the equalizer and decoder, thereby reducing silicon area. Further, by introducing block-interleaved computation in the add-compare-select recursions, the critical path delay is reduced thereby improving throughput. Experinicntal results with QPSK modulation and I<3 3 encoder demonstrate that the proposed area-efficient architecture achieves area savings of 47% with l l% throughput gain i n 0.25 p m CMOS process. It is also shown that the throughput is improved by 79% via block-interleaved computation with an area savings of 25%.